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Description: 用Verilog语言写的FPGA FIFO,仅供参考。-Verilog language used to write the FPGA FIFO, for informational purposes only.
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Size: 1024 |
Author: yangyu |
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Description: SDRAM的vegilog代码,做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
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Size: 717824 |
Author: 吴厚航 |
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Description: 用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
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Size: 141312 |
Author: liping |
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Description: 精通verilog HDL语言编程源码之8——异步FIFO设计-Proficient in language programming verilog HDL source of 8- Asynchronous FIFO Design
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Size: 2048 |
Author: 李平 |
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Description:
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Size: 545792 |
Author: john |
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Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
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Size: 6144 |
Author: 韩冰 |
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Description: 比较完整的LCD接口代码,verilog编写,分为6800和8080两种CPU接口,且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
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Size: 1831936 |
Author: 李佳 |
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Description: FIFO存储电路的设计与实现,用verilog实现fifo的参考设计-FIFO memory circuit design and realization of the realization of fifo with Verilog reference design
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Size: 186368 |
Author: jeff |
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Description: 先入先出缓冲存储器,采用verilog hdl-FIFO buffer memory, using verilog hdl
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Size: 2048 |
Author: 江浩 |
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Description: verilog编写的异步fifo源代码,asyn_fifo.v为顶层,调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
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Size: 2048 |
Author: nihao |
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Description: 使用Verilog硬件描述语言完成了一个异步FIFO的设计,供相关硬件开发人员参考。-Verilog hardware description language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
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Size: 3072 |
Author: 小米 |
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Description: FIFO级联,利用verilog语言实现Xilinx FIFO18单元的多个级联,增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
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Size: 3072 |
Author: blackmew |
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Description: verilog语言实现,利用BlockRAM实现FIFO。-Verilog language, the use of BlockRAM achieve FIFO.
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Size: 3072 |
Author: blackmew |
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Description: 先进先出缓存器的verilog设计与实现-design of fifo(first in first out)
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Size: 492544 |
Author: 杨毕辉 |
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Description: 使用Verilog编写的同步FIFO,可通过设置程序中的DEPTH设置FIFO的深度,FIFO_WRITE_CLOCK上升沿向FIFO中写入数据,
FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising edge to the FIFO write data, FIFO_READ_CLOCK rising edge of read data. This procedure on the upper FIFO operation simple and practical.
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Size: 1024 |
Author: 张键 |
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Description: 实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能,简单易懂,并带有相应的测试文件-Fifo realize the basic functions. Be able to use the Verilog implementation of the synchronous data FIFO functions, easy to understand, with the corresponding test file
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Size: 1024 |
Author: 汪艳婷 |
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Description: 异步FIFO的FPGA实现,XILINX FPGA,
ISE ,VHDL语言实现-asynchronous fifo
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Size: 75776 |
Author: Denny |
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Description: A Verilog description of a synchronous FIFO memory circuit
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Size: 1024 |
Author: balloo |
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Description: 利用Verilog实现了一个FIFO,包含几个模块文件,适合初学Verilog的朋友,含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
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Size: 4096 |
Author: speed |
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Description: Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
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Size: 846848 |
Author: Lokous |
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